1. Field of the Invention
The present invention relates to a semiconductor circuit. More specifically, it relates to a semiconductor circuit, which allows a timing adjustment after detailed routing without rearrangement and rerouting by using primitive cells (variable delay cells) including a built-in means that adjusts delay time, and which is utilized for cell-based designs.
2. Description of the Related Art
In a conventional synchronous dynamic random access memory (SDRAM), data writing and reading can be successively performed in sync with an external clock while switching banks, which are provided by dividing a memory cell array into multiple banks. Furthermore, a memory operating at a high-speed data rate, such as a double data rate SDRAM (DDR-SDRAM) capable of operating at a double data transfer rate, has recently been in the mainstream. However, an application requiring a random cycle such as a network system needs to accelerate operations in the same bank. A double data rate fast cycle random access memory (DDR-FCRAM) resolves this problem. A DDR-FCRAM is capable of being successively written and read at a high speed in sync with an external clock in units of banks provided by dividing a memory cell array into multiple banks. A DDR-FCRAM is useable for an application such as a network system because it is capable of not only transferring data at a double data rate, but also carrying out a high-speed random cycle operation implemented through improvement of memory cell array operations or using a new writing system.
A DDR interface (I/F), a clock generating circuit and the like require strict timing adjustment. That amount of adjustment is often less than the buffer delay time of a primitive cell. With conventional technology, interconnects are deliberately diverted and relevant cells are deliberately rearranged at long a distance. Therefore, troublesome overheads of rerouting, re-extraction, delay time recalculation and the like occur. Furthermore, not only can the effects of that adjustment not be known until executed, but there may be adverse affects to other portions as well. Moreover, this adjustment method can basically only increase delay, and is equivalent to not having an adjustment method for reducing delay.
A DDR I/F requires strict timing adjustment. For example, there is a constraint where changes in 64-bit data signal arrival time must be within ±150 picoseconds (ps). Even if this constraint is imposed on a conventional engineering design (EDA) tool, it is difficult to be satisfied, thereby requiring manual fine adjustment by analyzing the results from that tool. For example, fine adjustment such as delaying Data [0] by 30 ps and, expediting Data [1] by 40 ps or the like is carried out. However, since the buffer delay value of the primitive cell is about 100 to 200 ps according to a 130 nm process, signal arrival time cannot be delayed by adding a buffer. Thus, delay needs to be adjusted by deliberately diverting interconnects, which increases interconnect capacitance. In order to expedite the signal arrival time, the interproximal interconnect capacitance is reduced by placing a single open track and forming relevant interconnects, or cells are rearranged so that the interconnect lengths can be shortened; however, the results thereof are insignificant. In the case of insufficient improvement in the timing, relaxing constraints or restarting from routing may be necessary. Relaxing constraints may cause wider margins and a decrease in yield, and restarting from routing delays design completion.
An ASIC including multiple clock drivers, which are arbitrarily connectable to a clock signal line and have different correctable driving capabilities (transistor channel widths), is disclosed in Japanese Patent Application Laid-open No. 2001-111391 (see FIGS. 4, 5, 12, and 13).
A delay time adjustment cell library and a delay time adjustment method allows adjustment of off timings without rearrangement and rerouting. This is accomplished by using a delay time adjustment cell library for a group of interconnect cells that include basic cells, transistor cells with multiple basic cells, and interconnect patterns, each connecting between devices within a basic cell or between basic cells. See Japanese Patent Application Laid-open No. 2001-230324, for example.
However, an objective of Japanese Patent Application Laid-open No. 2001-111391 is to adjust a hold margin for clock delay and adjustment of variance due to process variation is not considered. Furthermore, both Japanese Patent Application Laid-open No. 2001-111391 and Japanese Patent Application Laid-open No. 2001-230324 are for making a delay adjustment before or during the process, and do not consider delay adjustment after chip formation.